Switching
Circuits and Logic Design (CS21002, 3-1-0)
Venue: NR-223, Nalanda Complex
** IMPORTANT INSTRUCTIONS **
LAB QUIZ TEST ON APRIL 16, 2014 (WEDNESDAY)
:: 3:00 PM to 4:30 PM
END-SEMESTER SYLLABUS :: K-map and Q-M
method of minimization, flip-flops and their realizations, sequential circuit
synthesis and minimization, register and counter designs, binary decision diagrams (BDD), logic design using
NAND/NOR gates, MUX, PLA
Course Outline:
Switching Circuits. Logic families: TTL, nMOS, CMOS,
dynamic CMOS and pass transistor logic (PTL) circuits, inverters and other
logic gates, area, power and delay characteristics, concepts of fan-in, fan-out
and noise margin.
Switching theory: Boolean algebra, logic gates, and
switching functions, truth tables and switching expressions, minimization of
completely and incompletely specified switching functions, Karnaugh map and
Quine-McCluskey method, multiple output minimization, representation and
manipulation of functions using BDDs, two-level and multi-level logic circuit
synthesis.
Combinational logic circuits: Realization of Boolean
functions using NAND/NOR gates, decoders, multiplexers. Logic design using
ROMs, PLAs and FPGAs. Case studies.
Sequential
circuits: clocks, flip-flops, latches, counters and shift registers.
Finite-state machine model, synthesis of synchronous sequential circuits,
minimization and state assignment, asynchronous sequential circuit synthesis.
ASM charts: Representation of sequential circuits using ASM charts, synthesis
of output and next state functions, data path control path partition-based
design.
1.
Z. Kohavi and N.K. Jha, “Switching and Finite Automata
Theory”, Cambridge University Press, 2010.
Important Instructions:
·
Attendance in the
classes is mandatory. If the attendance of some student falls below 75% at any
time after February 7, 2014, he/she will be deregistered from the course.
·
Assignments will be uploaded
on the web site on a regular basis. Students are expected to solve the
assignments off-line, and clarify doubts (if any) during the classes.
·
The breakup of marks
will be as follows:
o
30%: Mid-semester
examination
o
50%: End-semester
examination
o
20%: Class tests
·
Classes will be mostly
conducted using chalk-board. Official slide sets and miscellaneous study
materials from some of the main text books will be uploaded on the web site on
a regular basis.
·
Every student is
expected to have access to at least the book by Kohavi & Jha.
Lecture Slides: (mainly from the book by Kohavi & Jha)
Sl. No. |
Topic |
Slides / Resources |
Assignments |
1. |
Number systems and codes |
||
2. |
Switching algebra |
||
3. |
Minimization of switching expressions |
||
4. |
Logic design for combinational circuits |
||
5. |
Binary decision diagrams |
||
6. |
Synchronous sequential circuits |
||
7. |
Sequential circuit minimization |