VLSI System Design (CS60067, 3-1-0)
Venue: Room-107, CSE Department (Ground Floor)
Syllabus for End-Semester Examination (26/11/2018, 2:00PM – 5:00PM, CSE-107 & CSE-108):
· Simple delay analysis (without using logical effort)
· Dynamic CMOS logic
· Latch and flip-flop design
· Design styles
· Partitioning, Floorplanning and Placement
· Routing: Grid, Global and Detailed
Introduction to VLSI Design, Different types of VLSI design styles: Full custom, standard cell based, gate array based, programmable logic, field programmable gate arrays etc.
VLSI Design flow. CMOS logic: PMOS, NMOS and CMOS, Electrical characteristics, operation of MOS transistors as a switch and an amplifier, MOS inverter.
Stick diagram, design rules and layout, delay analysis.
Different types of MOS circuits: Dynamic logic, BiCMOS, pass transistors etc. CMOS process, Combinational logic cells, Sequential logic cells, Datapath logic cells, I/O cells. Logical effort, gate array, standard cell and datapath cell design.
Memristor-based logic design: design styles, crossbar implementation.
Introduction to hardware description language (HDL) Verilog/VHDL. A logic synthesis example.
Floor-planning and Placement: I/O and power planning, clock planning. Routing: global and detailed. Example design technique: mapping of architecture to silicon.
1. D.A. Pucknell and K. Eshraghian, Basic VLSI Design, PHI Learning Private Limited, 2013.
2. N.H.E. Weste, D. Harris and A. Banerjee, CMOS VLSI Design: A Circuits and Systems Perspective, Third Edition, Pearson, 2006.
3. M.J.S. Smith, Application Specific Integrated Circuits, Addison-Wesley Pub. Co., 1997.
4. J. Bhasker, Verilog HDL Synthesis: A Practical Primer, B.S. Publications, 1998.
5. N.A. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, 1999.
6. Online MOOC Course on Verilog, http://onlinecourses.nptel.ac.in/noc18_cs48/preview
Materials for download:
1. Assignment 1 (Familiarization with SPICE) pdf
2. Assignment 2 (Familiarization with Verilog) pdf
1. VLSI design styles pdf
2. Partitioning pdf
3. Floorplanning pdf
4. Placement pdf
1. Attendance in the classes is mandatory. If the attendance of some student falls below 75% at any time after August 22, 2019, he/she will be deregistered from the course.
2. The course will consist of laboratory and take-home assignments, which has to be done very seriously. If a student does not submit the assignments, his/her grade will remain as incomplete.
3. Some of the laboratory assignments will be conducted in the Advanced VLSI Design Laboratory, Takshashila Building, where exposure to commercial CAD tools will be made.
4. The breakup of marks will be as follows:
o 30%: Mid-semester examination
o 40%: End-semester examination
o 20%: Assignments
o 10%: Class tests
5. Classes will be mostly conducted using chalk-board. Miscellaneous study materials will be uploaded on the web site as and when required.