Lectures

1. Lecture 1

2. BDD from Book

Further class notes will NOT be available online in PPT format.

Assignments

1. Assignment 1 (SUBMISSION CLOSED)

2. Assignment 2 (SUBMISSION CLOSED)

3. Assignment 3

Assignment Helps

1.Cadence Tutorial for Circuit Simulation

2.Cadence User Guide

Course Outline:

1. Basics of MOS circuits:

• MOS Transistor structure and device modeling

• MOS Inverters

• MOS Combinational Circuits - Different Logic Families

2. Sources of Power dissipation:

• Dynamic Power Dissipation

  1. Short Circuit Power

  2. Switching Power

  3. Gliching Power

• Static Power Dissipation

• Degrees of Freedom

3. Supply Voltage Scaling Approaches:

• Device feature size scaling

• Multi-Vdd Circuits

• Architectural level approaches: Parallelism, Pipelining

• Voltage scaling using high-level transformations

• Dynamic voltage scaling

• Power Management

4. Switched Capacitance Minimization Approaches:

• Hardware Software Tradeoff

• Bus Encoding

• Two's complement Vs Sign Magnitude

• Architectural optimization

• Clock Gating

• Logic styles

5. Leakage Power minimization Approaches:

• Variable-threshold-voltage CMOS (VTCMOS) approach

• Multi-threshold-voltage CMOS (MTCMOS) approach

• Dual-Vt assignment approach (DTCMOS)

• Transistor stacking

6. Special Topics:

• Adiabatic Switching Circuits

• Battery-aware Synthesis

• Variation tolerant design

Text/Reference Books:

T1. Sung_Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, Tata Mcgrag Hill

T2. Neil H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2^nd Edition, Addison Wesley (Indian reprint).

T3. A. Bellamour, and M. I. Elmasri, Low Power VLSI CMOS Circuit Design, Kluwer Academic Press, 1995

T3. Anantha P. Chandrakasan and Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995

R1. Kaushik Roy and Sharat C. Prasad, Low-Power CMOS VLSI Design, Wiley-Interscience, 2000

Evaluation:

Mid-term : 30%

End-term : 50%

Term Assessment : 20%