Low Power VLSI Research Group @ IIT Kharagpur |
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Research activities |
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BDD based Synthesis and Testing for VLSI Circuits
Binary Decision Diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits. In this paper, we have proposed a new BDD-based approach for the synthesis of dual-rail adiabatic MUX circuits. The method yields around 22% reduction in the number of MUX blocks for several benchmark circuits compared to the conventional approach. Simulation result using SPICE on 180 nm technology shows, on an average, 50% reduction in power consumption for frequency ranging up to 300 MHz compared to implementation with static CMOS MUX circuits. At 600 MHz, power saving is observed to be nearly 35%. It is envisaged that the proposed approach will be useful in realizing low-power circuits.
Researchers: Sambhu Nath Pradhan | Gopal Paul | Prof. Bhargab B. Bhattacharya | Prof. Ajit Pal Yield aware low power synthesis Dual VT along with sizing has been found to be a very effective technique for leakage power minimization in CMOS circuits. However, the use of dual-VT not only involves higher cost of realization; it also leads to lower yield due to process parameter variations. This paper presents a novel yield-aware approach for leakage power minimization. By making more effective use of sizing, the proposed approach provides comparable reduction in leakage power by using single threshold voltage. It provides lower cost of implementation and higher yield compared to dual-VT. Low Power Sensor Node for a Wireless Sensor Network
Electronic devices like sensor nodes which are also called as motes are getting smaller, but their battery charge density is not getting increased in the same ratio. Since the life of a sensor network depends on the life of the sensor nodes, the lifetime of the sensor nodes have to be maximized. This can happen if the battery lasts long. In this paper, we introduce a power aware sensor node architecture and a battery-aware task scheduling algorithm that uses both Dynamic Voltage Scaling (DVS) and Reverse Body Biasing (RBB) to maximize the battery life time. Researchers: Sujan Kundu | Sravan Akepati | Prof. Ajit Pal Design and implementation of a FPGA based portable system for ecg signal acquisition, processing and monitoring Electrocardiogram (ECG) is the most commonly used biomedical signal for diagnostic purpose. It can be used to diagnose heart disease, identify cardiac arrhythmias, and evaluate effect of drugs. In this paper, the design and implementation of a FPGA based system and the techniques used to delineate the ECG signal are presented. We are designing and implementing a FPGA based system for clinical use. It can be used to acquire ECG signal from the patient and display it on a graphical LCD. The signal is analyzed to delineate PQ, QRS and ST complexes and derive parameters like heart beat rate and PR, PQ and QT intervals. There are several options to transfer the data from our system to a computer. The data can be stored in a USB thumb drive, which in turn can be sent to the desired location. The system can be directly connected to a local computer through the USB port. It can also be connected to a remote computer using a dial-up connection through an external modem. The system adheres to the standards and protocols specified by HL7.
Researchers: Prashant Agrawal | Prof. Ajit Pal Low power techniques for DSP circuit synthesis
The DSP circuits are data intensive. We are trying to use some power optimization techniques during high-level synthesis of those circuits to reduce the dynamic power significantly. Thus, the total power of such circuits can also be reduced. There are several loop transformation techniques like loop unrolling, loop folding, tree height reduction, loop expansion applicable to DSP algorithms for pipelining. They are also used to reduce dynamic power of the corresponding architecture. Here is a scope to reduce the total power consumed by the DSP circuits. Analysis of process parameter variations in low power design
As the technology is scaled down, process parameter variations have become severe problem for low power design also. The process parameter are channel length, oxide thickness, threshold voltage, doping concentration in the channel. The variations of these process parameters are expected to be significantly larger in future generations. As a result, the yield of the circuit will be less. The variation of leakage power and delay in the transistors on a given die are different for different low power design techniques. So, the yield analysis is very impoertant. The low power design technique should be such that it is less sensitive to the process parameter variations.
Researchers: Sudip Roy | Ashish Tiwari | Prof. Ajit Pal High-Level Synthesis for Low Power Due to the decrease in the device feature size, the power consumption density is increasing. This is hindering portability and requires more cooling. This also disturbs the stability of the circuits. So, optimizing power consumption has become the area of concern, encouraging design for low power. It has been found that power can be more effectively optimized at higher levels of VLSI Design methodology. In this direction, the present project is concerned with optimizing power at the High-Level Synthesis Stage of Design.
Researchers: Sudip Roy | Arundhati Jana | Prof. Ajit Pal |
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Low Power Adiabatic Logic Circuits Low power is the increasing concerned in today’s VLSI circuits. Efficient Adiabatic circuit is used to reduce power consumption in the VLSI circuits. The term “adiabatic” is used to indicate that all charge transfer is to occur without generating heat. Adiabatic switching allows the recycling of energy to reduce the total energy drawn from the power supply. Researchers: Sambhu Nath Pradhan | Sudip Roy | Sujan Kundu | Prof. Ajit Pal |
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Design and development of a CAD tool for RUBDD and ROBDD generation, having applications
in VLSI logic synthesis, testing and verification The CUDD tool is an open source package to generate
the ROBDD from a given Boolean function in its
canonical form. BDD can also be gererated using ratio parameter algorithm that is either unordered or ordered. Sysnthesis, Verification and Testing can be performed efficiently on this ratio-parameter based BDD.
Researchers: Gopal Paul | Samir Satpathy | Ashish Tiwari | Prof. Ajit Pal |
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Methodology for Instruction Set Extension of Embedded Processors
There is a growing demand for application-specific embedded processors. Current tools and design methodologies often require designers to manually specialize the processor based on an application. Moreover, the use of the new complex instructions added to the processor is often left to designers' ingenuity. In our proposed research work, we want to develop methodology that automates
The main focus of this methodology would be energy optimization under performance and area constraints. This methodology will improve designer's productivity and efficiently customize an embedded processor for the given application such that the energy consumption is greatly improved.
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Copyright ©2006 LPV Research Group. All Rights Reserved. For suggestions and comments please contact: sudipr@cse.iitkgp.ernet.in Last modified on Thu, January 11, 2007 8:52 PM |
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