Low Power VLSI Research Group @ IIT Kharagpur

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2007  |  2006    |    2005    |    2004    |    2003    |    2002    |    2001    |    Archieves
 

2007

  • Tanmay De, Asutosh Kumar Pathak, Ajit Pal, "An Efficient Heuristic-based Algorithm for Wavelength Converter Placement in All-optical Networks", 14th IEEE International Conference on Telecommunications and Malaysia International Conference on Communications (ICT-MICC 2007), Penang, Malaysia.
  • Tanmay De, Soumen Kumar, Ajit Pal, "An Efficient Algorithm for Routing and Wavelength Assignment in All Optical Networks", International Conference on Advanced Computing and Communication (ICACC 2007), Madurai, India.
  • Akapeti Sravan, Sujan Kundu, Ajit Pal, "Low Power Sensor Node for a Wireless Sensor Network", 20th International Conference on VLSI Design, January 2007, Bangalore , India.

2006

  • Gopal Paul, Sambhu N. Pradhan, Bhargab B. Bhattacharya, Annapurna Das, Ajit Pal, "BDD-based Synthesis of Logic Functions Using Adiabatic Multiplexers", International Journal on Systemics, Cybernetics, and Informatics, vol. 1, pp. 44-49 (2006).
  • Gopal Paul, Sambhu N. Pradhan, Bhargab B. Bhattacharya, Ajit Pal, Annapurna Das, "BDD-based Synthesis of Logic Functions Using Adiabatic Multiplexers", International Conference on Systemics, Cybernetics and Informatics (ICSCI-2006), Hyderabad.
  • Gopal Paul, Sambhu N. Pradhan, Bhargab B. Bhattacharya, Ajit Pal, "Low-power BDD-based Logic Synthesis using Dual-rail Static DCVSPG Logic", IEEE Asia Pacific Conference on Circuit and System, December 2006, Singapore.
  • Gopal Paul, Ajit Pal, "High Speed Power Efficient CGIC Digital Filters for VLSI Applications", IEEE INDICON, India. September 2006.
  • A. Jana, Ajit Pal, "Yield Aware Approach For Low Power Synthesis", IEEE ICECE- 2006, Bangladesh.
  • Prashant Agrawal, Abhijeet Kumar, Ajit Pal, "Design and Implementation of a FPGA Based Portable Syatem for ECG Signal Acquisition, Processing and Monitoring", Indian Conference on Medical Informatics and Telemedicine, ICMIT 2006, IIT Kharagpur, India.
  • Sambhu N. Pradhan, Gopal Paul, Bhargab B. Bhattacharya, Ajit Pal, "Power Aware BDD-based Logic Synthesis Using Adiabatic Multiplexers", IEEE ICECE- 2006, Bangladesh.
  • A. Jana, A. Pal, "Sizing for Low Power", International Conference on Computer & Communication Engineering (ICCCE'06), Malyasia, May, 2006.
  • Gopal Paul, Bhargab B. Bhattacharya, Ajit Pal, "On Finding the Minimum Test Set of a BDD-based Circuit", ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI- 2006), Proceeding pp. - 169-172, Philadelphia, USA.

2005

  • Gopal Paul, Bhargab B. Bhattacharya, Ajit Pal, Annapurna Das, "A Graph Algorithm for Finding the Minimum Test Set of a BDD-based Circuit", The Asian Applied Computing Conference (AACC), LNCS, Springer Verlag, Nepal, 2005.
  • M. Marik, A. Pal, "Logic Synthesis and Technology Mapping of MUX-based FPGAs for Performance and Low Power", Proc. TENCON 2005, pp. 2702-2707, Melbourne, Australia, Nov. 2005.
  • P. Agrawal, A. Jana, A. Pal, “ECG Data Acquisition and Monitoring System for Telemedicine Application”, Indian Conference on Medical Informatics & Telemedicine, pp. 159-162, Kharagpur, February 2005.
 

2004

  • M. Marik, Ajit Pal, "Energy-aware Logic Synthesis and Technology Mapping for MUX based FPGAs", proc. 17th International Conference on VLSI Design, 2004, pp. 73-78, Mumbai,India, January 2004.
  • D. Samanta, Ajit Pal, "Synthesis of Low Power High Performance Dual-Vt PTL Circuits", proc. 17th International Conference on VLSI Design, 2004, pp.85-90, Mumbai, January 2004.
 

2003

  • D. Samanta, Ajit Pal, "Logic Styles for Low power High Performance", Proc. 12th International Workshop on Logic and Synthesis (IWLS), pp. 355-362, Laguna Beach, CA, USA, May 2003.
  • D.Samanta, M. C. Dharmadeep, Ajit Pal, "Synthesis of High Performance Low Power PTL Circuits", proc. ASP-DAC 2003, pp. 209-212, Kitakyusyu, Japan, January 2003.
  • D. Samanta, Ajit Pal, "Synthesis of Dual-VT Dynamic CMOS Circuits", proc. VLSI Design Conference 2003, pp. 121-128, New Delhi, January 2003.
 

2002

  • D. Samanta, Nishant Sinha, Ajit Pal, "Synthesis of High Performance Low Power Dynamic CMOS Circuits", Proc. 7th ASP-DAC/15th VLSI Design Conference, pp. 99-104, Bangalore, India, January 2002.
  • D. Samanta, Ajit Pal, "Optimal Dual-VT Assignment for Low Voltage Energy Constrained CMOS Circuits", Proc. 7th ASP-DAC/15th VLSI Design Conference, pp. 193-198, Bangalore, India, January 2002.
 

2001

  • N.Tripathy, A.Bhosle, D. Samanta, Ajit Pal, "Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits", Proc. of International Conference on VLSI Design, pp. 227-232, Bangalore, India, January, 2001.
 

Archieves

  • Amar Mukherjee, Ajit Pal, "Sythesis of Two-Level Dynamic CMOS Circuits", IEEE Proc. of International Workshop on Logic Synthesis, May 1999.
  • R.K. Gorai, V.V.S.S. Raju, Ajit Pal, "Synthesis of Multiplexer Network using Ratio Parameters and Mapping onto FPGAs", 8th Int. Conference on VLSI Design, pp. 63-68, New Delhi, January 1995.
  • R. K. Gorai, Ajit Pal, "State Assignment of Finite State Machines for Optimal Implementation using MUXs", proceedings of the IEEE Tencon '91, pp. 175-179, New Delhi, , August 1991.
  • R. K. Gorai, I. Sengupta, Ajit Pal, "Exaustive Testing of RP-Checksum as Signature", proceedings of the National Systems Conference, Aligarh, March 1991.
  • R. K. Gorai, I. Sengupta, Ajit Pal, "Ratio parameters: a new signature for exaustive testing", IEEE Proc., U.K., 1990.
  • R. K. Gorai, Ajit Pal, "Automated Synthesis of combinational circuits by cascade Networks of multiplexers", IEEE Proc., U.K., Part-E, Vol. 137, pp. 164-170, March 1990.
  • R. K. Gorai, Ajit Pal, "On Logic Design using Multiplexers", presented in the Prof. A. K. Choudhury Commemoration Symposium, University of Calcutta, India, February 1990.
  • R. K. Gorai, Ajit Pal, "Automated Synthesis of Combinational Circuits by Tree Networks of Multiplexers", proceedings of the 3rd International Conference on VLSI Design, pp. 300-305, Bangalore, India, January 1990.
  • Ajit Pal, "A New Approach for Cellular Realisation of TSC Chekers for m-out-of-n codes", proceedings of the 3rd International Conference on VLSI Design, pp. 173-178, Bangalore, India, January 1990.
  • P. K. Purkait, Ajit Pal, "A Microprocessor-based Air Condition Monitoring System", proceedings of the 13th National Systems Conference, NSC-89, pp. 90-93, Kharagpur, India, December 1989.
  • R. K. Gorai, I. Sengupta, Ajit Pal, "Ratio Parameters: A New Signature for Exhaustive Testing", proceedings of TENCON-89, 4th IEEE Region-10 Conference, pp. 897-900, Bombay, India, November 1989.
  • R. K. Gorai, Ajit Pal,"Automated Synthesis of Combinational Circuits by Cascade Networks of Multiplexers", proceedings of National Conference on Electronic Circuits and Systems, NACONECS-89, pp. 386-388, Roorkee, India, November 1989.
  • G. Biswas, Ajit Pal, "An Analog-to-RNS Converter for VLSI Implementation", proceedings of the platinum jubilee conference on Systems and Signal processing, pp. 388-390, IISC-Bangalore, December 1986.
  • Ajit Pal, "An Algorithm for Optimal Logic Design using Multiplexers", IEEE Trans. Comput., Vol. C-35, No. 8, pp. 755-757, USA, August 1986.
  • A. K. Sanyal, Ajit Pal, "A Microprocessor-based Temperature Monitoring and Control System", Students' journal of IETE, Vol. 26, No. 4, pp. 150-156, October 1985.
  • B. B. Bhattacharya, Ajit Pal, "Syndrome Testable Logic Design using DSTL Arrays for Detecting Stuck at and Bridging Faults", IEEE Proc., U.K., Vol. 132, Pt. E, No.5, pp.251-257, September 1985.
  • Ajit Pal, "A 4-variable Programmable Universal Logic Module using Digital Summation Threshold Logic Gates", proceeding of the IEEE, USA, Vol. 72, No. 12, pp. 1813-1815, December 1984.
  • A. K. Sanyal, Ajit Pal, "A Microprocessor-based ECG Monitoring System", proceedings of the 4th International Conference on Electronic Circuits, MICRO- ELECTRONICS '84, pp. 154-156, Czechoslovakia, September 1984.
  • B. B. Bhattacharya, Ajit Pal, "Easily Testable Logic Design using DSTL arrays", proceedings of the International FTSD '83 Conference, pp. 191-199, Czechoslovakia, September 1983.
  • H. K. Worah, M. K. Chakraborty, Ajit Pal, "A Microprocessor-based Annunciator System", Proceedings of the Computer Society of India Convention-83, Ahmedbad, April 1983.
  • Ajit Pal, "Logic Design using Digital Summation Threshold Logic Gates", IEEE Proc., UK, Vol. 130, Pt. E, No. 1, pp. 32-36, January 1983.
  • S. K. Basu, K. Sen, J. Dattagupta, Ajit Pal, "Microprocessor-based EPROM Programmer", presented at the International Conference on advances in Information Sciences and Technology, Calcutta, January 1982.
  • Ajit Pal, "Interface 12 or 16-bit DACs to an 8 bit Microcomputer", EDN, USA, pp. 163, November 25, 1981.
  • Ajit Pal, "Comparator Circuit Regulates Battery Charging Current", Electronics, USA, pp. 142, October 6, 1981.
  • Ajit Pal, "An Interative Algorithm for Testing 2-asummability of Boolean Functions", proceedings of the IEEE, USA, Vol. 69, No. 9, pp. 1164-1166, September 1981.
  • H. K. Worah, Ajit Pal, "Some Studies on 16-bit Microprocessor's Architecture", presented at the Institution of Electronics and Telecommunication Engineer's symposium, Calcutta, May 1981.
  • B. Chakrabarti, A. Mishra, Ajit Pal, "Microprocessor-based Line Frequency Monitoring System", proceedings of the Computer Society of India convention-81, pp. 137-144, New Delhi, March 1981.
  • A. Sen, M. K. Chakrabarti, J. Dattagupta, B. P. Sinha, P. K.Srimani, A. R. Dasgupta, Ajit Pal, "Microprocessor-based Special Purpose FFT Processor", proceedings of the Computer Society of India convention-81, pp. 129-136, New Delhi, March 1981.
  • A. Mishra, B. Chakrabarti, Ajit Pal, "Microprocessor-based Line Voltage Monitoring System", proceedings of the Computer Society of India convention-81, India, pp. 79-87, New Delhi, March 1981.
  • P. K. Srimani, B. P. Sinha, Ajit Pal, "Fail-Safe Realization of Sequential Machines with a new Two-level MOS Module", Computers and Electrical Engineering, USA, Vol. 7, pp. 163-173, 1980.
  • Ajit Pal, "Synchronous Sequential Machine Realization Using 2-level MOS Modules", proceedings of the Symposium on Mini-Micro Computers and Automation, pp. 3.1-3.14, University of Roorkee, India, March 1979.
  • Ajit Pal, "Synthesis of Non-threshold Functions using DSTL Gates", presented at the "Micro-79"  Symposium, Banaras Hindu University, India, January 1979.
  • R. K. Sen, A. K. Choudhury, Ajit PAl, "A Programmable Logic State Analyser", Journal of IETE, India, Vol. 23, No. 7, pp. 434-439, July 1977.
  • P. De, A. Sen, D. Sharma, A. K. Choudhury, Ajit PAl, "A New Approach for Testing and Realization of a Set of Boolean Functions by Variable-threshold Elements", presented at the Symposium of Circuits Systems and Computers, Calcutta, India, February 1975.
  • A. Palit, S. Pal, M. S. Basu and A. K. Choudhury, Ajit PAl, "Fault Detection in a Two-level Negative Gate Network", Journal of IETE, India, Vol. 21, No. 2, pp. 58-65, February 1975.
  • S. Bandyopadhyay, A. K. Choudhury, Ajit Pal, "Characterization of Unate Cascade Realizability Using Parameters", IEEE Trans. Comput., U.S.A., Vol. C-24, No. 2, pp. 218-219, February 1975.
  • P. De, A. Sen, D. Sharma, A. K. Choudhury, Ajit Pal, "Minimal Realization of Arbitrary Functions with 2-level Networks of Iso-distinct and Isobaric gates", Int. J. Systems Science, U. K., Vol. 5, No. 6, pp. 555-573, June 1974.
  • P. De, A. Sen, D. Sharma, A. K. Choudhury, Ajit PAl, "A Tabular Method for Finding 2-summable and Mutually 2- summable Pairs of Minterms", Int. J. Electronics, U.K., Vol.37, No.3, pp. 409-427, March 1974.
  • A. K. Choudhury, Ajit PAl, "Realization of Synchronous Sequential Machine Using threshold Gates", presented at the CASAMCU Research Symposium on Numerical and Combinational analysis, Calcutta, India, February 1974.

 

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