EE60100: Mixed Signal Circuits and Systems-on-Chip

Venue: In online teaching mode
Class Timings: WED(12:00-12:55) , THURS(11:00-11:55) , FRI(09:00-10:55)
Teaching Assistants (TAs): Aditi Chakraborty (aditichakraborty154 [AT] gmail [DOT] com), Ashish Kumar Jha (ajha111192 [AT] gmail [DOT]com)
References:
[1] Design of Analog CMOS Integrated Circuits by Bezad Razavi, Tata McGraw-Hill
[2] CMOS Analog Circuit Design by Allen and Holberg, Oxford Indian Edition
[3] Analog Integrated Circuit Design, (Second Edition) by Tony Chan Carusone, David Johns, Kenneth Martin, Wiley
[4] Nanoelectronic Mixed-Signal System Design, by Saraju P. Mohanty, McGraw-Hill
[5] System-On-A-Chip: Design and Test, by Rochit Rajsuman, Artech House Signal Processing Library
[6] CMOS VLSI Design, A Circuits and Systems Perspective, (Fourth Edition) by N. H. E. Weste and D. M. Haris, Pearson
    Class-1: Introduction to mixed signal circuits and system-on-chip
    Module-1: Single Stage Amplifiers
    Class-2: CMOS basic, V-I characteristics and different regions of operation [1]
    Class-3: Determining the region of operation, parasitic capacitances of MOS [1]
    Class-4: Small signal parameters of MOSFET, Common source amplifiers [1]
    Class-5: Common source with source degenration and its terminal impedances [1]
    Class-6: Common drain amplifier, common gate amplifier, Basic Current mirror [1]
    Class-7: Cascoded current mirror and wide swing cascode current mirror [1]
    Module-2: Differntial Amplifier
    Class-8: Develovement of differential amplifier with resistive load, large signal response, common mode response [1]
    Class-9: Differential gain, design trade-offs [1]
    Class-10: Differential amplifier with diode connected load and current mirror load, tutorial problem. [1]
    Class-11: Different design trade-offs in differential amplifier and tutorial problem. [1]
    Class-12: Tutorial problems
    Class-13: Tutorial on Cadence: Differential Amplifier Design.
    Module-3: Comparators
    Class-14: Dynamic characteristics of comparators, Push/Pull output stage/OTA comparator [2]
    Class-15: Two stage comparator, clamped comparator with enhanced gain [2]
    Class-16: Comparator with driving high capacitive load, tutorial problem, autozeroing technique and its implementation [2]
    Class-17: Tutorial on Cadence: Two stage Comparator Design.
    Class-18: Hysteretic Comparator [2]
    Class-19: Rail-to-rail Comparator Link
    Class-20: Tutorial on Cadence: Hysteretic Comparator Design.
    Class-21: Class Test
    Module-4: Physical/Layout Design
    Class-22: Layout of MOS transistor and different layers, metalization scheme, single tub versus twin tub process. [2]
    Class-23: Layout of digital gates
    Class-24: Layout of analog circuits, concept of matching. [2]
    Class-25: Common centriod layout, use of dummy transistors, common guidelines [2]
    Class-26: Layout of capacitor and resistor [2]
    Class-27: Latch-up issue [2], Tutorial on Cadence: Layout example: digital and analog layout
    Module-5: Operational Amplifiers
    Class-28: Specifications of op-amps [2], Telescopic/cascode op-amp [1]
    Class-29: Folded cascode op-amps [1]
    Class-30: Practical implementation of folded cascode op-amp, Two-stage uncompensated op-amp [2], Miller theorem [1]
    Class-31: Miller theorem, two-stage compensated op-amp. [2]
    Class-32: Controlling RHP zero, Design steps of two-stage op-amp [2]
    Class-33: Tutorial Problem
    Class-34: Class Test
    Class-35: Class Test
    Module-6: Essential Elements of Mixed-Signal System
    Mostly covered in the prerequisite course on Analog Signal Processing.
    Class-36: Implementation of ADC and DAC [2, 4]
    Class-37: Type-II/Charge-pump based phase locked loop [1, 4]
    Class-38: Dynamics modelling of CP-PLL, Implementation of Voltage Controlled Oscillator [1, 4]
    Module-7: Memory in Analog Mixed-Signal System-on-Chips (AMS-SoCs)
    Class-39: Memory hierarchy in a computing system, classifications of memory, SRAM array architecture [4]
    Class-40: 6T SRAM cells, read, write and cell stability, Sense Amplifier [4,6]
    Class-41: DRAM cell, write and read operation, DRAM array architecture, ROM architecture [4,6]
    Class-42: PROM, EPROM, EEPROM, Flash memory, NAND Architecture, erase, write and read operation [6]
    Module-8: Analog Mixed-Signal System-on-Chips (AMS-SoCs) Design
    Class-43: Example of an emerging AMS-SoC, essential components and challenges in design [4]
    Class-44: Top-down versus bottom-up approach on integrated design, Analog design flow. [4]
    Class-45: Digital circuit design flow, Concurrent mixed-signal circuit design flow [4], SoC design, classifications of SoC, classification of different cores [5]
    Class-46: Hardware-software co-design, General guidelines for design reuse in SoC [5], chip packaging options [6], Summary
    Class-47: Class Test
    Class-48: Class Test