EE60100: Mixed Signal Circuits and Systems-on-Chip

Venue: NC342 at Nalanda Class Complex (Shifted from NEX201 at EE)
Class Timings: WED(10:00-10:55) , THURS(09:00-09:55) , FRI(11:00-12:55)
Teaching Assistants (TAs): Aditi Chakraborty (aditichakraborty154 [AT] gmail [DOT] com) and Rohit Chaudhari (rrc2345 [AT] gmail [DOT] com)
References:
[1] Design of Analog CMOS Integrated Circuits by Bezad Razavi, Tata McGraw-Hill
[2] CMOS Analog Circuit Design by Allen and Holberg, Oxford Indian Edition
[3] Analog Integrated Circuit Design, (Second Edition) by Tony Chan Carusone, David Johns, Kenneth Martin, Wiley
[4] Nanoelectronic Mixed-Signal System Design, by Saraju P. Mohanty, McGraw-Hill
[5] System-On-A-Chip: Design and Test, by Rochit Rajsuman, Artech House Signal Processing Library
[6] CMOS VLSI Design, A Circuits and Systems Perspective, (Fourth Edition) by N. H. E. Weste and D. M. Haris, Pearson
    Class-1: Introduction to mixed signal circuits and systems
    Module-1: Revision of CMOS basics
    Class-2: Common source amplifier, Development of CMOS differential amplifier and its large signal response [1]
    Class-3: CMOS differential amplifier with resistive load, ICMR, small signal differential gain, [1]
    Class-4: Its small signal common mode gain, CMRR, design tips [1]
    Class-5: Tutorial on Cadence tool
    Class-6: CMOS differential amplifier with current mirror load, its large and small signal responses, ICMR, design tips [1]
    Module-2: Comparators
    Class-7: Comparator basics, static and dynamic characteristics of comparators [2]
    Class-8: Two stage comparator [2]
    Class-9: Push/Pull output stage/OTA comparator [2]
    Class-10: Cascode and Wide-swing current mirror to enhance output impedance [2]
    Class-11: Push/Pull output stage comparator with enhanced gain, Comparator with driving high capacitive load [2]
    Class-12: Auto-zeroing, Hysteretic Comparator [2]
    Class-13: Rail-to-rail Comparator Link
    Class-14: High Speed Comparator [2]
    Class-15: Tutorial on Cadence: Design example: Two-stage comparator, Home Assignment-1
    Class-16: Tutorial Problems
    Module-3: Operational Amplifiers
    Class-17: Specifications of op-amps [2], Single-stage op-amps [1]
    Class-18: Telescopic/cascode op-amp [1]
    Class-19: Folded-cascode op-amp [1]
    Class-20: Tutorial
    Class-21: Miller theorem [1], Two-stage uncompensated op-amp [2]
    Class-22: Frequency compensation [2]
    Class-23: Design of two-stage op-amp [2], Tutorial Problem
    Class-24: Tutorial on Cadence: Design example: Two-stage op-amp Home Assignment-2
    Module-4: Physical/Layout Design
    Class-25: Layout of MOS transistor and different layers, Layout of digital gates [2]
    Class-26: Layout of analog circuits, matching, common centriod layout [2]
    Class-27: Use of dummy transistors, capacitor and resistor layout, metal routing [2]
    Class-28: Tutorial on Cadence: Layout example: Digital and analog block, Tutorial Problem
    Module-5: Essential Elements of Mixed-Signal System
    Mostly covered in the prerequisite course on Analog Signal Processing. Here, we will learn few implementation examples
    Class-29: Electronic signal conversion circuits, Key specifications and implementation of ADC [2, 4]
    Class-30: Key specifications and implementation of DAC [2, 4]
    Class-31: Type-II/Charge-pump based phase locked loop [1, 4]
    Class-32: Dynamics modelling of CPPLL [1, 4]
    Class-33: Implementation of Voltage Controlled Oscillator, Key specifications [1, 4] Home Assignment-3
    Module-6: Memory in Analog Mixed-Signal System-on-Chips (AMS-SoCs)
    Class-34: Memory hierarchy in a computing system, classifications of memory, SRAM array architecture [4]
    Class-35: SRAM cells, read, write and cell stability [4,6]
    Class-36: Sense Amplifier, DRAM array architecture [4,6]
    Class-37: DRAM cell, write and read operation, ROM architecture [4,6]
    Class-38: PROM, EPROM, EEPROM [6]
    Class-39: Flash memory, NAND Architecture, erase, write and read operation [6]
    Module-7: Analog Mixed-Signal System-on-Chips (AMS-SoCs) Design
    Class-40: Example of an emerging AMS-SoC, essential components and challenges in design [4]
    Class-41: Design perspective of AMS system, integrated circuit design flow: top-down versus bottom-up [4]
    Class-42: Top-down design flow [4]
    Class-43: Bottom-up design flow, Different level of abstrations in analog and digital designs [4]
    Class-44: Analog circuit design flow [4]
    Class-45: Digital circuit design flow [4]
    Class-46: Concurrent mixed-signal circuit design flow [4]
    Class-47: SoC design, classifications of SoC, classification of different cores [5]
    Class-48: Hardware-software co-design [5], chip packaging options [6]
    Class-49: General guidelines for design reuse in SoC [5]
    Class-50: Summary