Sponsored
Research:
Current
projects:
Formal verification
of state-event systems (Indian National Science Academy)
Verification in Virtual
Silicon (Virtio Corporation, USA)
Formal verification
of RTL (Sun Microsystems, USA)
Coverage analysis for
formal property verification (Intel, USA)
Developing OVA checkers
for verification of standard BUS protocols (Synopsys)
Previous
projects:
Study of applicability of decision diagrams
for logic evaluation (Synopsys Inc)
Study of static scheduling techniques for
event driven simulation (Synopsys Inc)
High Performance Local Area Multiprocessing
(Ministry of HRD, Govt. of India)
Advanced Techniques for Logic Evaluation (Synopsys
Inc)