Hardware Accelerated Constrained Random Test Generation

With the recent shift towards coverage driven randomized verification, complex test-benches tend to degrade the throughput of hardware accelerated simulation, motivating the synthesis of test-bench languages. The central task in this problem is that of randomized test generation under a given set of constraints in hardware. In this project, we present the first deterministic methods and tool for constrained random test generation in hardware. The  results on standard bus protocols (e.g. AMBA AHB, IBM CoreConnect) show the effectiveness of the approach. Here we provide two example constrained random test-benches (for IBM CC OPB Master and DCR Master Device) to show that our methodology can handle constraints used in the standard test-benches (at least at the protocol level).


 IBM CC OPB Master Test-Bench

 IBM CC DCR Master Test-Bench