Testing
and Verification of Circuits (CS60089, 3-1-0)
Venue: Room-119, CSE Department (Ground
Floor)
Course Outline:
Physical faults and their modeling. Fault equivalence and dominance; fault collapsing.
Fault simulation: parallel, deductive and concurrent techniques;
critical path tracing.
Test generation for combinational circuits: Boolean difference,
D-algorithm, PODEM, etc.
Exhaustive, random and weighted test pattern generation; aliasing and
its effect on fault coverage.
PLA testing: cross-point fault model, test generation, easily testable
designs.
Memory testing: permanent, intermittent and pattern-sensitive faults;
test generation.
Test pattern generation for sequential circuits: ad-hoc and structured
techniques; scan path and LSSD, boundary scan.
Built-in self-test techniques.
System-on-chip (SoC) testing. Low-power
testing. Delay fault testing.
Verification --- logic level (combinational and sequential circuits),
RTL-level (data path and control path).
Use of formal
techniques – decision diagrams, logic-based approaches.
1. M.L. Bushnell and V.D. Agrawal,
“Essentials of Electronic Testing”, Kluwer Academic
Publishers, 2000.
2. N.K. Jha and S. Gupta,
“Testing of Digital Systems”,
3. M. Abramovici, M.A. Breuer
and A.D. Friedman, “Digital Systems Testing and Testable Design”, Wiley-IEEE
Press, 1993.
4. P.H. Bardell, W.H. McAnney and J. Savir, “Built-in Test
for VLSI: Pseudorandom Techniques”, Wiley Interscience,
1987.
5. L-T. Wang, C-W. Wu and X. Wen,
“VLSI Test Principles and Architectures”, Morgan Kaufman Publishers, 2006.
6.
P.K. Lala, “Fault Tolerant and Fault Testable Hardware Design”,
Prentice-Hall Intl., 1985.
Benchmark Circuits:
ISCAS-89
Sequential Benchmarks tar archive
Important Instructions:
·
Attendance in the classes is mandatory. If the
attendance of some student falls below 75% at any time after August 16, 2013,
he/she will be deregistered from the course.
·
The course will consist of laboratory and take-home
assignments, which has to be done very seriously. If a student does not submit
the assignments, his/her grade will remain as incomplete.
·
Some of the laboratory assignments will be conducted
in the Advanced VLSI Design Laboratory, Takshashila
Building, where exposure to commercial CAD tools will be made. There will also
be an implementation-oriented design project which has to be coded in C/C++.
·
The breakup of marks will be as follows:
o 20%:
Mid-semester examination
o 40%:
End-semester examination
o 30%:
Assignments
o
10%: Class test
·
Classes will be mostly conducted using chalk-board.
Official slide sets and miscellaneous study materials from some of the main
text books will be uploaded on the web site on a regular basis.
·
Every student is expected to have access to at least
the book by Bushnell-Agarwal.
Lecture Slides:
|
Sl. No. |
Topic |
Slides |
Additional resources |
|
1. |
Introduction to testing |
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|
2. |
Fault modeling |
||
|
3. |
Logic simulation |
||
|
4. |
Fault simulation |
||
|
5. |
Testability measures |
||
|
6. |
Combinational test pattern generation |
||
|
7. |
Sequential test pattern generation |
||
|
8. |
Design for testability |
|
|
|
9. |
Built-in self-test |
||
|
10. |
Boundary scan standard |
|
|
|
11. |
Memory testing |