CAD for VLSI Design

SPRING 2014-15

Course Outline:

Introduction: VLSI design flow, challenges. Verilog/VHDL: introduction and use in synthesis, modeling combinational and sequential logic, writing test benches.

Logic synthesis: two-level and multilevel gate-level optimization tools, state assignment of finite state machines. Basic concepts of high-level synthesis: partitioning, scheduling, allocation and binding. Technology mapping.

Synthesis of reversible logic circuits.

Physical design automation. Review of MOS/CMOS fabrication technology. VLSI design styles: full-custom, standard-cell, gate-array and FPGA. Physical design automation algorithms: floor-planning, placement, routing, compaction, design rule check, power and delay estimation, clock and power routing, etc. Special considerations for analog and mixed-signal designs.

References:

1. R.H. Katz, “Contemporary logic design”, Addison-Wesley Pub. Co., 1993.

2. M.J.S. Smith, “Application-specific integrated circuits”, Addison-Wesley Pub. Co., 1997.

3. S. Ramachandran, “Digital VLSI systems design”, Springer, 2007.

4. M.L. Bushnell and V.D. Agrawal, “Essentials of Electronic Testing”, Kluwer Academic Publishers, 2000.

5. M. Abramovici, M.A. Breuer and A.D. Friedman, “Digital Systems Testing and Testable Design”, Wiley-IEEE Press, 1993.

6. J. Bhasker, “Verilog VHDL synthesis: a practical primer”, B S Publications, 1998.

7. D.D. Gajski, N.D. Dutt, A.C. Wu and A.Y. Yin, “High-level synthesis: introduction to chip and system design”, Kluwer Academic Publishers, 1992.

8. M. Sarrafzadeh and C.K. Wong, “An introduction to physical design”, McGraw Hill, 1996.

9. N.A. Sherwani, “Algorithms for VLSI physical design automation”, Kluwer Academic Publishers, 1999.

10. S.M. Sait and H. Youssef, “VLSI physical design automation: theory and practice”, World Scientific Pub. Co., 1999.

Lecture Slides:

Sl. No.	Topic	Slides (pdf)	Other Materials
1.	Introduction	pdf
2.	Verilog	pdf
3.	Logic Synthesis	pdf
4.	Technology Mapping	pdf
5.	High-Level Synthesis	pdf	Force-directed scheduling FACET-synthesis
6.	Synthesis of Reversible Logic		Transformation-based synthesis ROBDD to ESOP Transformation ESOP-based synthesis
7.	VLSI Design Styles	pdf
8.	Partitioning	pdf
9.	Floorplanning	pdf
10.	Placement	pdf
11.	Grid Routing	pdf
12.	Global Routing	pdf
13.	Detailed Routing	pdf
14.	Miscellaneous Routing	pdf
15.	Layout Compaction
16.	Other topics …