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Prof. Ajit Pal      

 

 

 

 

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Biography

Research

Teaching

Publications

Invited Talks

Consultancy
&
Advisory

Professional Activities

Students

 

 

   Publications

 

 

 

 

 

 

 

 

 

 

 

 

Books

  • Ajit Pal, 'Microprocessors: Principles and Applications', Tata McGraw - Hill Publishing Co.
    Ltd, 348 pages, 1990 (15th reprint, 2004).
  • Ajit Pal, 'Microcontrollers: Principles and Applications ', Prentice Hall India Ltd, 374 pages, 2011.
  • Sudip Roy and Ajit Pal,' Impact of Leakage Power Reduction on Parametric Yield', LAP LAMBERT Academic Publishers, 172 pages, January 2013.
  • Ajit Pal, 'Microcontrollers: Principles and Applications ', Prentice Hall India Ltd, 2nd Reprint, 2014.
  • Ajit Pal, 'Low Power VLSI Circuits and Systems', Springer, 2014.

Selected Publications

2014-2011|2010-2006|2005-2001|2000-1996|1995-1991|1990-1986|1985-1981|1980-1973

     2014-2011

  • 'Loop Unrolling with Fine Grained Power Gating for Runtime Leakage Power Reduction.’ 18th International Symposium on VLSI Design and Test (VDAT 2014), July 16-18, 2014, Coimbatore, India, 2014.

Co-Author: Sumanta Pyne

  • 'POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent.’ IEEE Transactions on Computer Aided Design on Integrated Circuits and Systems (TCAD), vol. 32, no. 11, November 2013.

Co-Authors: Aritra Hazra, Rajdeep Mukherjee, Pallab Dasgupta, Kevin Harer, Ansuman Banerjee and Subhankar Mukherjee

  • 'An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis.’ Journal of Low Power Electronics, Volume 9, Number 3, 2013.

Co-Authors: Rajdeep Mukherjee, Priyankar Ghosh and Pallab Dasgupta

  • 'Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence.', 17th International Symposium on VLSI Design and Test (VDAT 2013), July 27-30, 2013, Jaipur, India, Springer CCIS Vol 382, pp 83-93, 2013.

Co-Author: Sumanta Pyne

  • 'Formal Verification of Architectural Power Intent', IEEE Transaction on VLSI Systems (TVLSI), vol. 21, no. 1, pp. 78-91, January 2013.

Co-Authors: Aritra Hazra, Sahil Goyal and Pallab Dasgupta

  • 'Formal Verification of Hardware/Software Power Management Strategies', International Conference on VLSI Design (VLSID), 2013.

Co-Authors: Rajdeep Mukherjee, Pallab Dasgupta, and Subhankar Mukherjee

  • 'Multi-Objective Low-power CDFG Scheduling using Fine-Grained DVS Architecture in Distributed Framework', International Symposium on Electronic System Design (ISED), 2012.

Co-Authors: Rajdeep Mukherjee, Priyankar Ghosh, Neerati Sravan Kumar and Pallab Dasgupta.

  • 'Minimization Using Fine-grained DVS Architecture at 90nm Technology', Asia-Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), 2012.

Co-Authors: Rajdeep Mukherjee and Priyankar Ghosh

  • 'Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques', Journal of Low Power Electronics (JOLPE), vol. 8, no.5, pp. 604-623, December 2012.

Co-Author: Sumanta Pyne

  • 'A Multi-Objective Perspective for Operator Scheduling using Fine-Grained DVS Architectures', International Journal of VLSI design and Communication Systems (VLSICS), 2012.

Co-Authors: Rajdeep Mukherjee, Priyankar Ghosh and Pallab Dasgupta

  • 'Operator Scheduling Revisited: A Multi-Objective Perspective for Fine-Grained DVS Architecture', 2nd International Conference on Advances in Computing and Information Technology (ACITY), pp. 633-648, 2012.
    Co-Authors: Rajdeep Mukherjee, Priyankar Ghosh and Pallab Dasgupta
  • 'Traffic Grooming in WDM Mesh Networks: A Light Trail Implementation', Journal of Advanced Materials Research, vol. 433-440, pp. 3905-3909 January 2012.
    Co-Authors: Sukanta Bhattacharya, Puneet Jain, Tanmay De
  • 'Realization of Power Aware Software Prefetching as a Multi-Objective Optimization Problem', Second IEEE International Conference on Computer and Communication Technology, ICCCT-2011, Allahabad, India, pp. 253-259.

Co-Authors: Sumanta Pyne, Krishanu Ray

  • 'Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design', IEEE Computer Society Annual Symposium on VLSI, ISVLSI-2011, Chennai, India, pp. 345-346.

Co-Authors: Mallikarjuna Rao Nimmagadda

  • 'Distributed Dynamic Grooming Routing and Wavelength Assignment in WDM Optical Mesh Networks', Journal of Photonic Network Communication, vol. 21, No. 2, pp. 117-126, April 2011.

Co-Authors: Tanmay De, Puneet Jain

  • 'An Algorithm for Traffic Grooming in WDM Mesh Networks Using Dynamic Path Selection Strategy', ICDCN 2011, pp. 263-268.

Co-Authors: Sukanta Bhattacharya, Tanmay De

     2010-2006

  • 'Traffic grooming in WDM mesh networks using dynamic path selection strategy',WOCN 2010, pp 1-5, September 2010.

Co-Authors: Sukanta Bhattacharya, Tanmay De

  • 'Leveraging UPF-Extracted Assertions for Modeling and Formal Verification of Architectural Power Intent', Design Automation Conference (DAC), June 2010.

Co-Authors: Aritra Hazra, Srobona Mitra, Pallab Dasgupta, Debabrata Bagchi and Kaustav Guha

  • 'Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks
    based on clique partitioning'    , Journal of Photonic Network Communications, Feb. (2010).
    Co-Authors: Tanmay De, Indranil Sengupta
  • 'A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield
    Analysis Under Effective Channel-length Variation'    , Journal of Low Power Electronics,
    Vol. 6, No. 1, pp. 80-92 (2010).
    Co-Author: Sudip Roy
  • 'Credit Reputation Propagation: A Strategy to Curb Free-Riding in a Large BitTorrent
    Swarm',     International Conference on Distributed Computing & Network (ICDCN 2010),
    Kolkata, pp. 207-218, LNCS Vol. 5935/2010, Springer (2010).
    Co-Authors: Suman Paul, Subrata Nandi
  • 'Low-Power Microcontroller for Wireless Sensor Networks', TENCON ’09, Singapore.
    Co-Authors: Digvijay Singh, Sai Prashanth .S, Sujan Kundu
  • 'A Novel Approach for the Identification of Totally Symmetric Boolean Functions in the
    Application of Efficient System Design    ', IEEE/tttc IDT-2008, pp. 243-248.
    Co-Authors: Gopal Paul, Ashish Tiwari, C. R. Mandal
  • 'Low Power Design of On-line Testers for Digital Circuits Using State Encoding', IEEE/tttc IDT-2008, pp. 142-147.
    Co-Authors: Gopal Paul, Santosh Biswas, C. R. Mandal
  • 'Power-Delay Efficient Technology Mapping of BDD-based Circuits Using DCVSPG Cells',
    IEEE/tttc IDT-2008, pp. 123-128.
    Co-Authors: Gopal Paul, Rohit Reddy, Jyotirmoy Ghosh, Bhargab B. Bhattacharya, C. R. Mandal.
  • 'A Genetic Algorithm Based Approach for Traffic Grooming, Routing and Wavelength
    Assignment in Optical WDM Mesh Networks'    , Proceedings of 16th IEEE International
    Conference on Networks (ICON 2008), New Delhi, India, 12-14 December 2008.
    Co-Authors: Tanmay De, Puneet Jain and Indranil Sengupta.
  • 'A Power-Aware Wireless Sensor Network Based Bridge Monitoring System' Proceedings of
    16th IEEE International Conference on Networks (ICON 2008), New Delhi, India. 12-14
    December 2008.
    Co-Authors: Sujan Kundu and Sudip Roy
  • 'A Multi Objective Evolutionary Algorithm Based Approach for Traffic Grooming, Routing
    and Wavelength Assignment in Optical WDM  Networks    ', IEEE Region 10 Colloquium and
    3rd IEEE International Conference on Industrial and Information Systems (ICIIS 2008),
    pp. 452-463, 8-10 December 2008, Kharagpur, India.
    Co-Authors: Tanmay De, Puneet Jain and Indranil Sengupta.
  • Artificial Intelligence Approach to Test Vector Reordering for Dynamic Power Reduction
    during VLSI Testing    ', Proceedings of the IEEE TENCON 2008, Hyderabad,
    November 19-21, 2008.
    Co-Authors: Sudip Roy and Indranil Sengupta
  • 'Impact of Runtime Leakage Reduction Techniques on Delay and Power Sensitivity under
    Effective Channel Length Variations    ', Proceedings of the IEEE TENCON 2008, Hyderabad,
    November 19-21, 2008.
    Co-Authors: Sudip Roy
  • 'Why to use Dual-Vt, if Single-Vt serves the purpose better under Process Parameter
    Variations?    ', Proceedings of the Eleventh Euromicro conference on Digital System Design
    (DSD 2008), pp. 282-287, Italy, September 3-5, 2008.
    Co-Authors: Sudip Roy
  • 'Synthesis of DSP Circuits for Low Power using Multiple-Vdd, Gate-level Sized and
    Optimal-Vt Library    ', Proceedings of the Fifth International Conference on Systemics,
    Cybernetics and Informatics (ICSCI 2008), pp. 25-29, Hyderabad, January 2-5, 2008 and
    International Journal on Systemics, Cybernetics and Informatics (ISSN 0973-4864), pp.
    37-41, July, 2008.
    Co-Authors: Sudip Roy and Arundhati Jana
  • 'When and How Much Random Walkers should Proliferate for a Fast and Efficient Walk?',
    Indian Institute of Science (IISc) Centenary Conference on Managing Complexity in a
    Distributed System (MCDES 2008) , May, 2008, IISc, Bangalore.
    Co-Authors: Subrata Nandi, Niloy Ganguly.
  • 'Routing and Wavelength Assignment in all Optical Networks based on Clique Partitioning',
    9th International Conference on Distributed Computing and Networking (ICDCN 2008),
    LNCS 4904 (Springer-Verlag) pp. 452-463, 5-8 January, 2008, Kolkata, India.
    Co-Authors: Tanmay De and Indranil Sengupta.
  • 'On the Determination of Maximum Independent Set of Edges in a BDD for the Testing of
    VLSI Circuits    ', Accepted in WMSCI-2007, USA.
    Co-Authors: Gopal Paul, Bhargab B. Bhattacharya
  • 'A Graph Algorithm for Finding the Minimum Test Set of a BDD-based Circuit', Advances
    in Computer Science and Engineering: Reports and Monographs - 2007; World Scientific
    Press (ISSN: 1793-2416), pp. 382-386.
    Co-Authors: Gopal Paul, Bhargab B. Bhattacharya, A. Das.
  • 'An Efficient Heuristic-based Algorithm for Wavelength Converter Placement in All-optical
    Networks    ', 14th IEEE International Conference on Telecommunications and Malaysia
    International Conference on Communications (ICT-MICC 2007), pp. 186-190, Penang,
    Malaysia.
    Co-Authors: Tanmay De, Asutosh Kumar Pathak.
  • 'An Efficient Algorithm for Routing and Wavelength Assignment in All Optical Networks',
    International Conference on Advanced Computing and Communication (ICACC 2007), pp.
    24-27 Madurai, India.
    Co-Authors: Tanmay De, Soumen Kumar.
  • 'Low Power Sensor Node for a Wireless Sensor Network', 20th International Conference
    on VLSI Design, January 2007, Bangalore, India.
    Co-Authors: Akepati Sravan, Sujan Kundu.
  • 'Low-power BDD-based Logic Synthesis using Dual-rail Static DCVSPG Logic', IEEE Asia
    Pacific Conference on Circuit and System, December 2006, Singapore.
    Co-Authors: Gopal Paul, Sambhu N. Pradhan, Bhargab B. Bhattacharya.
  • 'High Performance and Area Efficient n-bit Tree Based Binary Squarer', IEEE VDAT-2006,
    pp. 247-252.
    Co-Authors: Gopal Paul and Samir Satpathy
  • 'Design and Implementation of a FPGA Based Portable Syatem for ECG Signal Acquisition,
    Processing and Monitoring    ', Indian Conference on Medical Informatics and Telemedicine,
    ICMIT 2006, IIT Kharagpur, India.
    Co-Authors: Prashant Agrawal, Abhijeet Kumar.
  • 'Power Aware BDD-based Logic Synthesis Using Adiabatic Multiplexers', IEEE ICECE- 2006, Bangladesh.
    Co-Authors: Sambhu N. Pradhan, Gopal Paul, Bhargab B. Bhattacharya.
  • 'Yield Aware Approach for Low Power Synthesis', IEEE ICECE- 2006, Bangladesh.
    Co-Author: A. Jana.
  • 'High Speed Power Efficient CGIC Digital Filters for VLSI Applications', IEEE INDICON,
    India. September 2006.
    Co-author: Gopal Paul.
  • 'On Finding the Minimum Test Set of a BDD-based Circuit', ACM/IEEE Great Lakes
    Symposium on VLSI (GLSVLSI- 2006), Proceeding pp. - 169-172, Philadelphia, USA.
    Co-authors: Gopal Paul, Bhargab B. Bhattacharya.
  • ‘Sizing for Low Power’, International Conference on Computer & Communication
    Engineering (ICCCE'06), proceedings of the ICCCE'06 pp. - 1259-1264 Malyasia, May
    2006.
    Co-author: A. Jana.
  • 'BDD-based Synthesis of Logic Functions Using Adiabatic Multiplexers', International
    Journal on Systemics, Cybernetics, and Informatics, vol. 1, pp. 44-49 (2006).
    Co-authors: Gopal Paul, Sambhu N. Pradhan, Bhargab B. Bhattacharya, Annapurna Das.

                                                                                                                                      Top

     2005-2001

·         ‘Logic Synthesis and Technology Mapping of MUX-based FPGAs for Performance and Low
Power ’, Proc. TENCON 2005, pp. 2702-2707, Melbourne, Australia, Nov. 2005.
Co-Author: M.Marik.

·         'A Graph Algorithm for Finding the Minimum Test Set of a BDD-based Circuit', accepted
in The Asian Applied Computing Conference (AACC), LNCS, Springer Verlag, Nepal, 2005.
Co-authors: Gopal Paul, Bhargab B. Bhattacharya, Annapurna Das.

·         'ECG Data Acquisition and Monitoring System for Telemedicine Application', Indian
Conference on Medical Informatics & Telemedicine, pp. 159-162, Kharagpur, February
2005.
Co-author: P. Agrawal, A. Jana.

·         'Energy-aware Logic Synthesis and Technology Mapping for MUX based FPGAs', Proc.17th
International Conference on  VLSI Design,  2004, pp. 73-78, Mumbai,  January 2004.
Co-author: M.Marik.

·         'Synthesis of Low Power High Performance Dual-Vt PTL Circuits', Proc. 17th International
Conference on  VLSI Design,  2004,pp.85-90, Mumbai,  January 2004.
Co-author: D.Samanta.

·         'Location Management and Paging using Mobility Pattern', Proc. 9thAsia-Pacific
Conference on Communication 2003, pp. 439-443, Malaysia, September 2003.
Co-author: M.Pandey.

·         'Logic Styles for High Performance and Low Power', Accepted for presentation in the 12th
International Workshop  on Logic and Synthesis, 2003    (IWLS-2003), May 2003.
Co-author: D.Samanta.

·         'Synthesis of High Performance Low Power PTL Circuits', Proc. ASP-DAC 2003, pp. 209-
212, Kitakyusyu, Japan, January 2003.
Co-authors: D.Samanta, M. C. Dharmadeep.

·         'Synthesis of Dual-VT Dynamic CMOS Circuits', Proc. VLSI Design 2003, pp. 121-128, New
Delhi, January 2003.
Co-author: D.Samanta.

·         'Synthesis of High Performance Low Power Dynamic CMOS Circuits', 15th International
Conference on VLSI Design and ASP-DAC, pp. 99-104, Bangalore, January 2002.
Co-authors: D.Samanta, Nishant Sinha.

·         'Optimal Dual-Vt Assignment for Low Voltage Energy Constrained CMOS Circuits', in the
joint 15th International Conference on  and ASPDAC / VLSI Design, pp. 193-198,
Bangalore, January 2002.
Co-author: D.Samanta.

·         'Fault Tolerant Scheduling in Shared Memory Symmetric Multiprocessor Based Real Time
Systems Using A Layered Architecture', Proceedings of the 4th International Conference
on Information Technology, CIT-2001, TMH publications, pp. 285-290, December 2001.
Co-authors: N.V.Satyanarayana, Rajib Mall.

·         'Fault Tolerant Scheduling in Hypercube Multicomputer Systems', Proceedings of the 9th
International Conference on Advanced Computing and Communications (ADCOM-2001)
pp. 5-12, December 2001 .
Co-authors: N.V.Satyanarayana, Rajib Mall.

·         'Fault Tolerant Scheduling in Distributed Real-Time Systems', Proceedings of the 2001
International Conference on Computer Networks and Mobile Computing, pp. 275-280,
Beizing, October 2001.
Co-authors: Rajib Mall, N.V.Satyanarayana.

·         'Dynamic Location Management with Variable Size location Areas', Proceedings of the
2001 International Conference on Computer Networks and Mobile Computing, pp. 73-78,
Beizing, October 2001.
Co-author: D.S.Khati.

·         'Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS
Circuits', in IEEE/ACM Proc. of 14th International Conference on VLSI Design, January
2001.
Co-authors: N.Tripathy, A.Bhosle, D. Samanta.

 

 

 

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     2000-1996

·         'Subtask Deadline Assignment and Scheduling of Real-time Tasks', Proceedings of the 3rd
International Conference on Information Technology, CIT-2000, TMH publications, pp
151-159, December 2000.
Co-authors: N.V. Satyanarayana, Rajib Mall.

·         'Sythesis of Two-Level Dynamic CMOS Circuits', in IEEE Proc. of International Workshop
on Logic Synthesis, May 1999.
Co-author: Amar Mukherjee.

·         'DDSCHED : A Distributed Dynamic Real-Time Scheduling Algorithm', Journal of parallel
and Distributed computing practics, Schedule to be published. March 1999.
Co-authors: Arup Bhattacharya, K.Ravindranath, R.Mall.

·         'Deadline Assignment in Multiprocessor-Based Fault-Tolerant Systems', Proceedings of
the HiPC  1999.
Co-authors: S.K.Kodase,N.V.Satyanarayana,R.Mall.

·         'Fault Tolerant Scheduling of Real-time Systems', ADComp 1998 Pune, December 1998.
Co-author: SVN Kalyan.

·         'An Algorithm for finding non-trivial lower bound for channel routing', Integration: A VLSI
journal, 1997.
Co-authors: R.K.Pal, S.P.Pal.

·         `DDSCHED : A Distributed Dynamic Real-Time Scheduling Algorithm', Accepted for
presentation at ADCOMP '97, Chennai, December 1997.
Co-authors: A. K. Bhattacharya, K. Rabindranath & R. Mall.

·         `An Algorithm for nding a Non-Trivial Lower bound for Channel Routing', Proceeding of
the 10th International Conference on VLSI Design, pp. 531-532, January 1997.
Co-authors: R. K. Pal and S. P. Pal.

·         `A Layered Real-Time System Using Hypercubes', Proc. of the 31st CSI Annual
Convention, Bangalore, October 1996.
Co-authors: N. V. Satyanarayana and Rajib. Mall.

·         `A Layered Architecture for Real-Time System', Microprocessor and Microsystems, Vol.
20, pp. 241-250, 1996.
Co-authors: N. V. Satyanarayana and R. Mall.

 

 

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     1995-1991

·         `Computing area and wire length efficient routes for Channels', Proc. of the 8th
International IEEE Conference on VLSI Design, pp. 196-201, Delhi, January 1995.
Co-authors: R. K. Pal and S. P. Pal.

·         `Synthesis of Multiplexer Network using Ratio Parameters and Mapping onto FPGAs', 8th
Int. Conference on VLSI Design, pp. 63-68, New Delhi, January 1995 .
Co-authors: R.K. Gorai and V.V.S.S. Raju.

·         `A General Graph Theoretic Framework for Track Assignment in Multi-Layer Channel
Routing', Proc. of the 8th International Conference on VLSI Design, pp. 202-207, Delhi,
January 1995.
Co-authors: R. K. Pal and S. P. Pal.

·         `Absolute Approximation for Channel Routing is NP-hard', Proceedings of the 4th National
Seminar on Theoretical Computer Science, pp. 28-39,  Kanpur, June 1994.
Co-authors: R. K. Pal and S. P. Pal.

·         `Minimize Wire Length in Multi-Layer Channel Routing', Silver Jubilee Workshop on
Computing and Intelligent Systems, pp. 170-188, IISc-Bangalore, October 1993 .
Co-authors: R. K. Pal and S. P. Pal.

·         `Resolving Horizontal Constraints and Minimizing Net Wire length for Multilayer Channel
Routing', The IEEE International Region-10 Conference (TENCON '93), Beijing, China,
October 1993.
Co-authors: R. K. Pal, A. K. Datta and S. P. Pal.

·         `On the Computational Complexity of Area and Wire-Length Minimization in Multi-layer
Channel Routing', 3rd NSTCS, pp. 103-119, I.I.T, Kharagpur, June 1993.
Co-authors: R. K. Pal and S. P. Pal.

·         `NP Completeness of Multi-Layer Channel Rouing and an efficient Heuristic', International
Conference on VLSI Design, pp. 80-93, Bombay, January 1993 .
Co-authors: R. K. Pal, S. P. Pal and A. K. Dutta.

·         `A Graph-based three-layer Channel Router', Presented at the National Symposium on
Opmization Techniques and Applications '92, Madurai, India, July 2-3, 1992.
Co-authors: R. K. Pal and S. Bose.

·         `An efficient Track Assignment Technique for Channel Routing', Proc. of the 2nd National
Seminer on Theoritical Computer Science, pp. 59-79, Calcutta. June 17-19, 1992.
Co-authors: R. K. Pal and A. K. Dutta.

·         `A Graph-theoritic Four-Layer Channel Router', Proc. of the 5th National Systems
Conference 1991, pp. 179-183, Roorkee, India, March 1992.
Co-authors: R. K. Pal and S. Bose.

·         `Intra-Row standard Cell Placement Algorithm for Cost Optimal Routing', Proc. of the 5th
National Systems Conference 1991, pp. 174-178, Roorkee, India, March 1992.
Co-authors: R. K. Pal and S. Bose.

·         `An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing', Proc. of the
VLSI Design '92, The 5th VLSI/IEEE International Conference on VLSI Design, pp. 259-
262, Bangalore, January 4-7, 1992.
Co-author: R. K. Pal.

·         `An Efficient Four-Layer Channel Routing Algorithm based on Graph Theoritical
Applications', Proc. of the International ASME Conference on Signals, Data and Systems,
pp. 43-54, New Delhi, December 9-11, 1991.
Co-author: R. K. Pal.

·         'An Efficient Two-Layer Channel Router Using Graph Applications', Proc. of the
International ASME Conference on Signals, Data and Systems, pp. 31-42, New Delhi,
December 9-11, 1991.
Co-author: R. K. Pal.

·         `A New Generalized Channel Router With Interchangeable Terminals: GYACRIT', Proc of
the International ASME Conference on Signals, Data and Systems, pp. 19-30, New Delhi,
December 9-11, 1991.
Co-author: R. K. Pal.

·         'State Assignment of Finite State Machines for Optimal Implementation using MUXs',
Proc of the IEEE Tencon '91, pp. 175-179, New Delhi, , August 1991.
Co-author: R. K. Gorai.

·         `The State of the Art of LAN Technology', Electronics Information & Planning, pp. 435-
452, pp. 496-508 and pp. 625-646 , May, June and August, 1991, respetively.

·         `A Graph-Theoritic Approach for Two-Layer Channel Routing', Proceedings of the
National Systems Conference, pp. 12-14, Aligarh, March 1991.
Co-authors: R. K. Pal and S. Bose.

·         `Exhaustive Testing of RP-Checksum as Signature', Proceedings of the National Systems
Conference, Aligarh, March 1991.
Co-authors: R. K. Gorai and I. Sengupta.

·         `An Efficient Interchangeable Switch Box Routing with Interchangeable Terminal',
Proceedings of the NCRTS, pp. 84-88, Indore, February 1991.
Co-authors: R. K. Pal and S. Bose.

·         `An Efficient Interchangeable Switch Box Router: A Genralized Study', Proceedings of the
4th CSI/IEEE Interntional Conference on VLSI Design, pp. 279- 280, New Delhi, January
1991.
Co-author : R. K. Pal.

 

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     1990-1986

·         Cellular Ralization of TSC checkers for error detecting codes', Proceedings of the IEEE
Region-10 conference on Computer and communication systems, pp. 687-691, Hong
Kong, September 1990.

·         `Ratio parameters: a new signature for exaustive testing', IEEE Proc., U.K.
Co-authors : R. K. Gorai and I. Sengupta.

·         `Automated Synthesis of combinational circuits by cascade Networks of multiplexers',
IEEE Proc., U.K., Part-E, Vol. 137, pp. 164-170, March 1990.
Co-author: R. K. Gorai.

·         `YACRIT: Yet another Channel Router With Interchangeable Terminals', Presented in the
Prof. A. K. Choudhury Commemoration Symposium, University of Calcutta, India, February 1990.
Co-authors: R. K. Pal and U. K. Bhattacharya.

·         `On Logic Design using Multiplexers', Presented in the Prof. A. K. Choudhury
Commemoration Symposium, University of Calcutta, India, February 1990.
Co-author: R. K. Gorai.

·         `Automated Synthesis of Combinational Circuits by Tree Networks of Multiplexers', Proc.
of the 3rd International Conference on VLSI Design, pp. 300-305, Bangalore, India,
January 1990.
Co-author: R. K. Gorai.

·         `A New Approach for Cellular Realization of TSC Checkers for m-out-of-n codes', Proc. of
the 3rd International Conference on VLSI Design, pp. 173-178, Bangalore, India, January
1990.

·         `A Microprocessor-based Air Condition Monitoring System`, Proc. of the 13th National
Systems Conference, NSC-89, pp. 90-93, Kharagpur, India, December 1989.
Co-author: P. K. Purkait.

·         `Ratio Parameters: A New Signature for Exhaustive Testing', Proc. of TENCON-89, 4th
IEEE Region-10 Conference, pp. 897-900, Bombay, India, November 1989.
Co-authors: R. K. Gorai and I. Sengupta.

·         `Automated Synthesis of Combinational Circuits by Cascade Networks of Multiplexers',
Proc. of National Conference on Electronic Circuits and Systems, NACONECS-89, pp. 386-
388, Roorkee, India, November 1989.
Co-author: R. K. Gorai.

·         `Distributed Database System on PCs using LAN', Proceedings of the IETE 32nd Technical
Convention, pp. 47-50, Madras, May 1989.
Co-author: B. K. Albert.

·         `A Co-processor Approach for Database Machines', Proceedings of the seminar on
Parallel Processing Systems and their Applications, December 1988, India.
Co-author: G. Shaw.

·         `A Database System on a Network', Proceedings of the Seminar on Parallel Processing
Systems and their Applications, December 1988, India.
Co-authors: N. Asokan, P. K. Fatepuria A. K. Majumder and G. Shaw.

·         `AGRADOOT: An Interpreter for a High-level Programming Language in an Indian Script',
Presented at the CSI-88 Convention, Madras, January 1988.
Co-authors: S. J. Nath and D. Chatterjee.

·         `High Performance Secondary Storage Processor for Data Base Machines', Proceedings
of the Interntional Symposium on Electronic Devices, Circuits and Systems, pp. 226-228,
Kharagpur, India, December 1987.
Co-author: G. Shaw.

·         `On the Design and Development of a Computer for Indian Languages', IETE Technical
Review, Vol. 3, No. 12. pp. 606-611, December 1986, India.
Co-authors: A. P. Agarwal and N. K. Agarwal.

·         `An Analog-to-RNS Converter for VLSI Implementation', Proceedings of the platinum
jubilee conference on Systems and Signal processing, pp. 388-390, IISC-Bangalore,
December 1986.
Co-author: G. Biswas.

·         `An Algorithm for Optimal Logic Design using Multiplexers', IEEE Trans. Comput., Vol. C-
35, No. 8, pp. 755-757, USA, August 1986.

·         `System Fault Diagnosis of n-cube Network by Reconfiguration', Proceedings of the 9th
International Conference on Fault-Tolerant Systems and Diagnostics, Brno,
Czechoslovakia, June 25 - 27, 1986.
Co-author : R. K. Sen.

·         `On the Design and Development of a Multilingual Computer for Indian languages',
Proceedings of the Computer Society of India Convention, Calcutta, India, January 1986.
Co-authors: A. P. Agarwal, N. K. Agarwala.

·         `A Speech Scrambler using Random Sign Alteration of Amplitude Samples for Use in
Voice Grade Networks', Journal of IETE, Vol. 32, No. 1, pp. 1-5, India, January 1986.
Co-authors: S. Rakshit and J. Das.

·         `Knowledge-based System for ECG Feature Extraction and Diagnosis', Presented in the
1986 International Conference on Pattern Recognition and Digital techniques, Calcutta,
January 1986.
Co-authors: A. Maulik and S. Bhowmik.

 

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     1985-1981

·         `A Microprocessor-based Temperature Monitoring and Control System', Students' journal
of IETE, Vol. 26, No. 4, pp. 150-156, October 1985.
Co-author: A. K. Sanyal.

·         `Syndrome Testable Logic Design using DSTL Arrays for Detecting Stuck at and Bridging
Faults', IEEE Proc., U.K., Vol. 132, Pt. E, No.5, pp.251-257, September 1985.
Co-author: B. B. Bhattacharya.

·         `Microprocessor-based Temperature Controller', Proceedings of the Seminar on
Computer and Industry, Naini, Allahabad, pp. 315- 318, January 1985.
Co-author: A. K. Sanyal.

·         `Simulation Studies and Performance Analysis of a Relational Database Machine: REDAM',
Proceedings of the International Conferrence on Computers, Systems and Signal
Processing, pp. 1671-1675, Bangalore, India, December 1984.
Co-authors: B. K. Dutta, A. N. Rao, C. R. Rao and A. K. Majumdar.

·         `A 4-variable Programmable Universal Logic Module using Digital Summation Threshold
Logic Gates', Proceeding of the IEEE, USA, Vol. 72, No. 12, pp. 1813-1815, December
1984.

·         `A Microprocessor-based ECG Monitoring System', Proceedings of the 4th International
Conference on Electronic Circuits, MICRO- ELECTRONICS '84, pp. 154-156,
Czechoslovakia, September 1984.
Co-author: A. K. Sanyal.

·         `Easily Testable Logic Design using DSTL arrays', Proceedings of the International FTSD
'83 Conference, pp. 191-199, Czechoslovakia, September 1983.
Co-author: B. B. Bhattacharya.

·         `Interface 12 or 16 bit ADCs to a 8-bit Microprocessors', EDN, USA, pp. 243-244, May
26, 1983.

·         `System Diagnosability in Composite Systems', Proceedings of the IEEE ISCAS '83,
California USA, May 1983.
Co-authors: S. Ghosh, B. P. Sinha, J. Dattagupta and B. B. Bhattacharya.

·         `A Microprocessor-based Annunciator System', Proceedings of the Computer Society of
India Convention-83, Ahmedbad, April 1983.
Co-authors: H. K. Worah and M. K. Chakraborty.

·         `Logic Design using Digital Summation Threshold Logic Gates', IEEE Proc., UK, Vol. 130,
Pt. E, No. 1, pp. 32-36, January 1983.

·         `Microprocessor-based EPROM Programmer', Presented at the International Conference
on advances in Information Sciences and Technology, Calcutta, January 1982.
Co-authors: S. K. Basu, K. Sen and J. Dattagupta.

·         `Interface 12 or 16-bit DACs to an 8 bit Microcomputer', EDN, USA, pp. 163, November
25, 1981.

·         `Comparator Circuit Regulates Battery Charging Current', Electronics, USA, pp. 142,
October 6, 1981.

·         `An Interative Algorithm for Testing 2-asummability of Boolean Functions', Proceedings
of the IEEE, USA, Vol. 69, No. 9, pp. 1164-1166, September 1981.

·         `Some Studies on 16-bit Microprocessor's Architecture', Presented at the Institution of
Electronics and Telecommunication Engineer's symposium, Calcutta, May 1981.
Co-author: H. K. Worah.

·         `Microprocessor-based Line Frequency Monitoring System', Proceedings of the Computer
Society of India convention-81, pp. 137-144, New Delhi, March 1981.
Co-authors: B. Chakrabarti and A. Mishra.

·         `Microprocessor-based Special Purpose FFT Processor', Proceedings of the Computer
Society of India convention-81, pp. 129-136, New Delhi, March 1981.
Co-authors: A. Sen, M. K. Chakrabarti, J. Dattagupta, B. P. Sinha, P. K.Srimani and A. R.
Dasgupta.

·         `Microprocessor-based Line Voltage Monitoring System', Proceedings of the Computer
Society of India convention-81, India, pp. 79-87, New Delhi, March 1981.
Co-authors: A. Mishra and B. Chakrabarti.

 

 

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     1980-1973

·         `Fail-Safe Realization of Sequential Machines with a new Two-level MOS Module',
Computers and Electrical Engineering, USA, Vol. 7, pp. 163-173, 1980.
Co-authors: P. K. Srimani and B. P. Sinha.

·         `Pseudo-random Generator has Programmable Sequence length', Electronics, USA, Vol.
7, pp. 129, October 11, 1979.

·         `Synchronous Sequential Machine Realization Using 2-level MOS Modules', Proceedings of
the Symposium on Mini-Micro Computers and Automation, pp. 3.1-3.14, University of
Roorkee, India, March 1979.

·         `Synthesis of Non-threshold Functions using DSTL Gates', Presented at the "Micro-79"
Symposium, Banaras Hindu University, India, January 1979.

·         `A Programmable Logic State Analyser', Journal of IETE, India, Vol. 23, No. 7, pp. 434-
439, July 1977.
Co-authors: R. K. Sen and A. K. Choudhury.

·         `A New Approach for Testing and Realization of a Set of Boolean Functions by Variable-
threshold Elements', Presented at the Symposium of Circuits Systems and Computers,
Calcutta, India, February 1975.
Co-authors: P. De, A. Sen, D. Sharma and A. K. Choudhury.

·         `Fault Detection in a Two-level Negative Gate Network', Journal of IETE, India, Vol. 21,
No. 2, pp. 58-65, February 1975
Co-authors : A. Palit, S. Pal, M. S. Basu and A. K. Choudhury.

·         `Characterization of Unate Cascade Realizability Using Parameters', IEEE Trans.
Comput., U.S.A., Vol. C-24, No. 2, pp. 218-219, February 1975.
Co-authors: S. Bandyopadhyay and A. K. Choudhury.

·         `Minimal Realization of Arbitrary Functions with 2-level Networks of Iso-distinct and
Isobaric gates', Int. J. Systems Science, U. K., Vol. 5, No. 6, pp. 555-573, June 1974.
Co-authors: P. De, A. Sen, D. Sharma and A. K. Choudhury.

·         `A Tabular Method for Finding 2-summable and Mutually 2- summable Pairs of Minterms',
Int. J. Electronics, U.K., Vol.37, No.3, pp. 409-427, March 1974.
Co-authors: P. De, A. Sen, D. Sharma and A. K. Choudhury.

·         `Realization of Synchronous Sequential Machine Using Threshold Gates', Presented at the
CASAMCU Research Symposium on Numerical and Combinational analysis, Calcutta, India, February 1974.
Co-author: A. K. Choudhury.

·         `A Simple Digital Capacitance Meter ', Journal of IETE, India, Vol.9, No. 3, pp. 659-662,
December 1973.
Co-authors: A. K. Basu and A. K. Choudhury.

·         `A Digital Phase-meter ', Journal of the Institution of Instrumentation Scientists and
Technologists, India, Vol. 2, No. 3, pp. 5-8, July 1973.
Co-authors: S. Bandyopadhyay and A. K. Choudhury.

 

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Department of Computer Science & Engineering
Indian Institute of Technology Khargpur

For suggestions and comments: Prof. Ajit Pal
Last modified on Mon, March 11, 2013 10:57 AM